FT232RL as a clock for a Acex EP1K50TC144-3 fpga

Hi Alex,

Thanks for the reply! Happy New year!

Fpga VCC_CLK pin 53 is connected to 3V3

I got a clock at 6Mhz, but when I set the FT232RL at 12Mhz output, my clock is there but seams to be unstable? I removed the 560ohm pull-up.

The input fpga Pin125 (Dedicated Clock Pin at FT232 out 48Mhz) is also connected to pin 126 (Dedicated Input) I want to divide my clock by 4 (48/4= 12Mhz) and send it to pin 55 (Dedicated Clock Pin=12Mhz) to divide it for my rs232 I/O baud clock (12/64=187500 baud)

Higher than 6Mhz reduces my input voltage levels to the fpga clock input. Any other ideas?

I assumed the fpga input needed a pull-up?

Thanks