FT2232H in Sync FIFO Mode - TXE# stuck high

Hi,

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Have you checked the obvious, TXE# is connected to an FPGA input pin and not an output being driven high?

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Already checked, I proceeded the same way (with a different name of pin obviously, according to the datasheet) with TXE# and RXF# and RXF# works perfectly.

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Have you tried clearing the transmit buffer with FT_Clear()?

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If by FT_Clear you mean FT_Purge without success, I've tried this (can't find any FT_Clear in the D2XX Programmer's guide).

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Have you actually issued an FT_Read()? Does the FT_Read() come back with an error, timeout, etc? What is your host system/OS?

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I can call FT_Read() without any error but I will always have 0 BytesReceived (even if I ask to read several bytes), which is kind of normal because FT_GetQueueStatus always says there is nothing in the receiving buffer.

TXE# high telling me the ft2232h is never ready to receive any data.

I'm on Windows7 (32-bit).

I load my fpga by USB through the channel B of my fifo with the MorphLd Utility, could this be somehow related?

Edit : loading fpga by JTAG doesn't change anything.

Many thanks for your help, I'm kind of new to this whole thing.

Alexis

Hi,

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Check here http://electro-logic.blogspot.it/2014/03/fpga-comunicazione-ad-alta-velocita_99.html?m=1

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I've already checked this useful blog, but I can't find what I did differently in my Software part, which I suppose being where my problem come from (receiving buffer not ready to receive).

I'm using D2XX drivers and not libftdi this shouldn't make a huge difference...

Here are my actions when trying to configure my device :

- FT_OpenEx

- FT_ResetDevice

- FT_Purge

- FT_SetBitMode - Reset Mode

- FT_SetBitMode - Sync FIFO Mode

- FT_SetLatency - 2ms

- FT_SetUSBParameters (64 Bytes each)

- FT_setTimeOuts

Alexis

Hi,

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Do you realize that in Sync FIFO mode the FT2232 is a single channel device? When you load your fpga through channel B it must somehow reconfigure the FT2232 for dual channel mode. Are you sure you're switching back to single channel when you try to run in sync FIFO mode?

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I'm not sure to fully understand what you mean, I'm sure to use channel B to load my FPGA (with MorphLd utility) and then I use a little GUI made with CVI-LabWindows where I only connect to channel A.

I manage to have the clock at 60mhz from the fifo in my fpga and the rxf# working fine make me think it's not a problem of channels.

Alexis

Hi,

The EEPROM seems right, the Software part too, and I have tested on an other Morph-IC-II to be sure there is no short circuit or bad solder.

I'm a bit lost again, I don't where to look or what to try anymore.

Thank you again for your help and ideas.

Alexis

Here's some of the code I used to configure channel A for sync fifo mode. Maybe something will stand out.

UCHAR Mask_A = 0xff; // all outputs

UCHAR Mode_A = 0x40; // high speed synchronous fifo

UCHAR Reset_Mode = 0x00;

UCHAR LatencyTimer = 2;

// connect with Channel A and set Mode

ftStatus = FT_Open(device_number_a, &FTDIHandle_A);

FT_SetBitMode(FTDIHandle_A, 0xff,Reset_Mode);

Delay(.01);

FT_SetBitMode(FTDIHandle_A, Mask_A,Mode_A);

FT_SetLatencyTimer(FTDIHandle_A, LatencyTimer);

FT_SetUSBParameters(FTDIHandle_A,65536,65536);

FT_SetFlowControl(FTDIHandle_A,FT_FLOW_RTS_CTS,0x00,0x00);

FT_SetTimeouts(FTDIHandle_A, 5000, 5000);

I'm using approximately the same, just trying with smaller buffers (64 bytes) to have something working first.

Do you know when your TXE# goes low, after which step ? Because mine is low at the beginning, goes high when the mode is set to sync fifo, and then never goes low, no matter what I'm doing.

Alexis.