FSM problem

Heyy I'm trying to make a video game in vhdl on de0 board and I need help about the following FSM. No error or warning. Does anyone notice a mistake??

type XY_REG_TYPE is array (0 to 19,0 to 9) of std_logic;
	type AB_REG_TYPE is array (0 to 3,0 to 3) of std_logic;
	type XY_NEXT_TYPE is array (0 to 19,0 to 9) of std_logic;
	type AB_NEXT_TYPE is array (0 to 3,0 to 3) of std_logic;	
	type STATE_TYPE is (count,zero,left,down,right);
	signal m : integer range 0 to 9;
	signal n : integer range 0 to 19;
	signal c,d : integer range 0 to 3;
	signal ab_reg : AB_REG_TYPE;
	signal xy_reg : XY_REG_TYPE;
	signal ab_next : AB_NEXT_TYPE;
	signal xy_next : XY_NEXT_TYPE;
	signal state_reg, state_next : STATE_TYPE;
	signal T_reg, T_next : integer range 0 to 10; 
	begin
        FSM1: process (clk, reset, n, m, c ,d)
		begin
			if reset = '1' then
				xy_reg(n,m) <= '0';
				T_reg <= 0;
				state_reg <= zero;
			elsif clk'event and clk = '1' then
				xy_reg(n,m) <= xy_next(n,m);
				T_reg <= T_next;
				state_reg <= state_next;
			end if;
		end process FSM1;
		
      FSM2: process (SW(1), BUTTON, xy_reg, ab_reg, state_reg, T_reg, T_next, m, n, c ,d)	
		begin
			xy_next(n,m) <= xy_reg(n,m);
			T_next <= T_reg;
			state_next <= state_reg;
			
			case state_reg is
			when count =>
				if EndOfField = '1' then
					T_next <= T_reg + 1;
					if T_reg = 10 and SW(1) = '1' then
						state_next <= zero;
					else
						state_next <= count;
					end if;
				end if;
			when zero =>
				if BUTTON = "111" then
					if xy_reg(n+1,m) = '0' then
						xy_next(n,m) <= xy_reg(n+1,m);
						T_next <= 0;
						state_next <= count;
					else
						xy_next(n,m) <= xy_reg(n,m);
						T_next <= 0;
						state_next <= count;
					end if;
				elsif BUTTON = "101" then
					state_next <= down;
				elsif BUTTON = "110" then
					state_next <= right;
				elsif BUTTON = "011" then
					state_next <= left;
				end if;
			when down =>
				if xy_reg(n+1,m) = '0' then
					xy_next(n,m) <= xy_reg(n+1,m);
					T_next <= 0;
					state_next <= count;
				else
					xy_next(n,m) <= xy_reg(n,m);
					T_next <= 0;
					state_next <= count;
				end if;	
			when right =>
				if xy_reg(n,m+1) = '0' then
					xy_next(n,m) <= xy_reg(n,m+1);
					T_next <= 0;
					state_next <= count;
				else
					xy_next(n,m) <= xy_reg(n,m);
					T_next <= 0;
					state_next <= count;
				end if;
			when left =>
				if m >= 1 then
					if xy_reg(n,m-1) = '0' then
						xy_next(n,m) <= xy_reg(n,m-1);
						T_next <= 0;
						state_next <= count;
					else
						xy_next(n,m) <= xy_reg(n,m);
						T_next <= 0;
						state_next <= count;
					end if;
				else
					xy_next(n,m) <= xy_reg(n+1,m);
					T_next <= 0;
					state_next <= count;
				end if;
			end case;
                 end process FSM2;