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Altera_Forum
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Honored Contributorfsm debuging
fsm debugging
Hi I started to check the fsm on real time and got some strange behaviors. I tried working with SignalTap but I didn't like the way he display the waves and we didn't really get how to work with him. So I went to ModelSim and created a test bench and got the next wave form There is a lot of signals there but I can see that the logic is working, the only problem is that the pwm is not working (the signal in red) and I don't know why. This design works when all the code is in the same file (without components) I had the same thing with the encoder enable nut I succeeded in solving it by giving him a default value of '0'. for another way to look were the program got stuck I used a 7 seg display where at the commands bk,fd - 1,2 the fsm got stuck at state 15 and in the commands rt,lt - 3,4 the fsm got stuck at state 1033 Replies
Altera_Forumyou can always output a "ready" or "valid" signal from your state machine to enable other reigsters.
- Altera_Forum
I have a problem implamenting your idea of matching pipeline
the max number of cycles int the pwm is 100000 so if I am going for pipeline length match should I enter a delay in the fsm for 100000 cycles... I want the signals from the component to come out to the device while they genrated not after a 100000 cycles delay as you can see in the next part of the fsm code I am waiting in the same state untill I am geting the encoder approval that will come after the pwm reg finishing his count and start turnnig the servo untill the wanted distancePwmReg: process (Clk,Rst) begin if (Rst='0') then Counter <= (others=>'0'); Pwm <='0'; elsif rising_edge(Clk) then if (Enable='1') then if (Counter = duty_cycle) then Counter <= (others => '0'); else Counter <= Counter + 1; end if; if (pulse_length > Counter) then Pwm <= '1'; else Pwm <= '0'; end if; end if; end if; end process PwmReg;
as for the idea with the flags I also having poblems because the pwm signal from the component is going through the fsm design out to the motor so where will I put the flags... for every pwm signal change I will rise a flag and then in the fsm design I will control the servo with a different signal?when execute_st => state_number1 <= 5; state_number2 <= 1; if (S_FSM_M_E_CEn = bit_high) and (S_FSM_M_E_En = bit_high) and (S_FSM_M_P_CEn = bit_high) and (S_FSM_M_P_En = bit_high) then M_P_En <= bit_high; M_E_En <= bit_high; if (S_M_E_done = bit_high) then S_FSM_M_P_pulse_length <= neutral_cycle; next_st := stop_st; else next_st := execute_st; end if; elsif (S_FSM_M_E_CEn = bit_low) and (S_FSM_M_E_En = bit_low) and (S_FSM_M_P_CEn = bit_low) and (S_FSM_M_P_En = bit_low) then S_FSM_M_P_pulse_length <= neutral_cycle; next_st := stop_st; else next_st := execute_st; end if; - Altera_Forum
1. Yes. All it increases is the latency. The throughput is still the same.
2. Yes. If you dont know how long something takes, consider using interal "valid" or "ready" signals to flag when a process has completed. - Altera_Forum
is sync reg are the best solution for pipeline length match because they causing the all process to take a longer amount of time.
And should I count in every component how much clocks he needs in order to finish the process and then take that into account in the fsm design - Altera_Forum
sync registers will lengthen pipleines. And you should know how long the pipelines are because you made them.
- Altera_Forum
What do you mean exactly when you said
do I do that with a sync reg like I did or in another way? how do I know that the pipe length is match ?ensure the pipeline lengths match along all paths - Altera_Forum
The synthesisor wont balance your paths for you. You still need to ensure the pipeline lengths match along all paths.
- Altera_Forum
I have putted an sync reg consisted from 3 FF and it's solved the problem
I thought that a component is a part of the system there for If the system is synchronized I don't need a sync reg between like I need in the case of getting data from the real world like a sensor... am I right? I am sorry in asvance for posting my every thought - Altera_Forum
The enable signals problem was solved earlier by giving them a reset value in the fsm design ( I guess I forgot)
For the pwm signals I have posted another picture of the problem according to the modelsim Do I need to put a flip-flop between internal signal that connects to the real world like in the case of the pwm component (pwm signal ) and the fsm design (M_P_signal,S_P_PWM) In order to synchronized between them? - Altera_Forum
thanks for your replay
--- Quote Start --- Better yet, have someone else do it (independent verification). Jerry --- Quote End --- well I have no one to check my design because I started to learn VHDL a few months ago by writing codes to a project I am doing and the people here help me a lot with every question I didn't succeeded on solving by myself , with a book or with Google. should I look in the component for the problem or in the fsm ... has i said before and your answer strengthen my believe that the problem is at the component and not in the fsm because when I put everything in one file it's working ( most of it any way I will solve the rest later on)
