fsm debuging

I have a problem implamenting your idea of matching pipeline

PwmReg: process (Clk,Rst)
begin
  if (Rst='0') then
    Counter <= (others=>'0');
    Pwm <='0';
  elsif rising_edge(Clk) then
 if (Enable='1') then
  if (Counter = duty_cycle) then
   Counter <= (others => '0');
  else
   Counter <= Counter + 1;
     end if; 
  if (pulse_length > Counter) then
   Pwm <= '1';
  else
   Pwm <= '0';
  end if;
 end if;
   end if;
end process PwmReg;

the max number of cycles int the pwm is 100000 so if I am going for pipeline length match should I enter a delay in the fsm for 100000 cycles...

I want the signals from the component to come out to the device while they genrated not after a 100000 cycles delay

as you can see in the next part of the fsm code I am waiting in the same state untill I am geting the encoder approval that will come after the pwm reg finishing his count and start turnnig the servo untill the wanted distance

    when execute_st =>
     state_number1 <= 5;
     state_number2 <= 1;
    if (S_FSM_M_E_CEn = bit_high) and (S_FSM_M_E_En = bit_high) and (S_FSM_M_P_CEn = bit_high) and (S_FSM_M_P_En = bit_high) then
      M_P_En <= bit_high;
      M_E_En <= bit_high;
      if (S_M_E_done = bit_high) then
       S_FSM_M_P_pulse_length <= neutral_cycle;
       next_st := stop_st;
      else
       next_st := execute_st;
      end if;
     elsif (S_FSM_M_E_CEn = bit_low) and (S_FSM_M_E_En = bit_low) and (S_FSM_M_P_CEn = bit_low) and (S_FSM_M_P_En = bit_low) then
      S_FSM_M_P_pulse_length <= neutral_cycle;
      next_st := stop_st;
     else 
      next_st := execute_st;
     end if;

as for the idea with the flags I also having poblems because the pwm signal from the component is going through the fsm design out to the motor

so where will I put the flags...

for every pwm signal change I will rise a flag and then in the fsm design I will control the servo with a different signal?