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Altera_Forum
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8 years ago

FSM Caught in impossible State

Hey all, So I've been developing an FPGA (Cyclone 3 Series) that basically sits between an FX3 USB 3 micro-controller and the HPI interface of a DSP. My problem lies withing my FSM, that is res...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

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Actually yes - it would need to be high for 2 clocks to work properly.

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I'd rather say there is a design error: because next_state is registered before being assigned to current_state, making mult_sig_done high for 2 clocks is 'plastering over the cracks'. But you can have the last word ...