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Altera_Forum
Honored Contributor
Honored ContributorFSM Caught in impossible State
Hey all, So I've been developing an FPGA (Cyclone 3 Series) that basically sits between an FX3 USB 3 micro-controller and the HPI interface of a DSP. My problem lies withing my FSM, that is res...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- This would only be the case if the mult_done_sig was not synchronised properly into the same clock domain as the state machine, Or it failed timing (and you havent checked timing) --- Quote End --- No, Tricky, that is not the case here. Perhaps read my previous post?
