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Altera_Forum
Honored Contributor
Honored ContributorFSM Caught in impossible State
Hey all, So I've been developing an FPGA (Cyclone 3 Series) that basically sits between an FX3 USB 3 micro-controller and the HPI interface of a DSP. My problem lies withing my FSM, that is res...
Altera_ForumHonored Contributor
Honored ContributorHave you got a test bench?
have you verified it works in simulation? How have you done this? Are all state machine inputs synchronised safely into the same clock domain? Verifiying it with scope and test pins is going to be a very slow and painful process.
