Frequent loss of transceiver CDR lock

Hi Sachin,

As I understand it, you have some inquiries related to the CDR lose lock-to-data. For your information, the following are general cause of CDR lose lock causes for your reference and to further debug into:

1. No valid signal present or there is an issue with signal integrity which violate the RX input specs. You may try to probe the eye diagram using oscilloscope to check on the Eye diagram quality. Then perform PMA tuning to see if it helps. You may also try to enable internal serial loopback to see if CDR can lock?

2. The ppm difference between the CDR refclk and incoming data clock domain exceed the configured ppm frequency threshold setting.

3. The CDR output clock and the input reference clock are not phase matched within approximately 0.08 unit interval (UI) (phase locked).

4. You may also want to ensure the CDR refclk and the mgmt_clk are directly sourced from free-running oscillators on board and with correct frequencies to isolate any power up calibration related issues.

Please let me know if there is any concern. Thank you.

Chee Pin