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Altera_Forum's avatar
Altera_Forum
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11 years ago

frequency stability of clk output from pll

for example,pll input clk is 10Mhz, from an OCXO oscillator,with a frequency stability 1ppb per day.

pll output clk is 10Mhz*10 = 100Mhz.

how to get the frequency stability information of the 100Mhz?

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    By nature of a PLL, the long term stability of the PLL output will be equal to that of the reference frequency. Non-ideal behaviour of a PLL shows at a short time scale. You probably want to review the respective FPGA hardware handbook about the PLL jitter specification.