Frequency of operation of M9K bram

Hello Dave and rbugalho,

I somehow needed to get the RAM inferred.

Dave...I tried what you told me to do in your previous post. When I instantiated the altsyncram component instead of my generic verilog code, M9K blocks are being inferred. I also tried wrapping the simple dual port RAM instead of the 2W4R RAM[ I have pasted the code below] in the test harness and synthesizing it. But I am facing the same problem.

module my_memory_blocks(

output reg [7:0] q,

input [7:0] d,

input [5:0] write_address, read_address,

input we,clk );

reg [7:0] mem [511:0];

always @ (posedge clk) begin

if (we)

mem[write_address] <= d;

q <= mem[read_address];

end

endmodule

When I click on the "Info (276004): RAM logic "my_memory_blocks:m0|mem" is uninferred due to inappropriate RAM size" it is pointing to the line in red in the above code. I cannot understand what is inappropriate in it even after following all the altera coding standards. I guess I will go ahead and file a service request as you said.