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Altera_Forum
Honored Contributor
12 years agoHi rbugalho,
Thank you so much for the reply. Kindly find attached the modules of the RAM. 1) The module named MEM_2w4r.v is the entire RAM design. - This when synthesized alone , M9K blocks were inferred. 2) The module named test_harness.v is the test harness which is used to wrap the RAM design. The compilation report gave this message : Info (276014): Found 4 instances of uninferred RAM logic Info (276004): RAM logic "MEM_2w4r:m0|MEM_1w4r:MEM_1|MEM_1w1r:MEM_1w1r_0|memory" is uninferred due to inappropriate RAM size Info (276004): RAM logic "MEM_2w4r:m0|MEM_1w4r:MEM_1|MEM_1w1r:MEM_1w1r_1|memory" is uninferred due to inappropriate RAM size Info (276004): RAM logic "MEM_2w4r:m0|MEM_1w4r:MEM_1|MEM_1w1r:MEM_1w1r_2|memory" is uninferred due to inappropriate RAM size Info (276004): RAM logic "MEM_2w4r:m0|MEM_1w4r:MEM_1|MEM_1w1r:MEM_1w1r_3|memory" is uninferred due to inappropriate RAM size The RAM is used in Simple dual port mode, with depth = 256 and width = 32. Please suggest how I can overcome the issue.