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I am having trouble with inferring RAM blocks when it is instantiated in another module.
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The RAMs should be inferring altsyncram components. The altsyncram blocks have internal input and output registers. If you are somehow accidentally connecting some of your other logic to what is effectively the output of the RAM input registers, then you might be upsetting the inference.
I would recommend placing the RAM interference code inside its own component. If you've done that already, and are still seeing this issue, then I would upload a code example, or file a Service Request with Altera.
Since you have to write tool-specific syntax to get inference working, I see no advantage over just instantiating an altsyncram directly. If you need portable VHDL, then you can always use configurations.
Cheers,
Dave
Honored Contributor
