Frequency of operation of M9K bram

Thanks so much for your replies. Helped me with the issue I was facing.

I am having trouble with inferring RAM blocks when it is instantiated in another module. When I synthesize the RAM design alone, the M9K blocks are inferred. But when I wrap the RAM in a test harness and synthesize it , the blocks aren't inferred! The top level module has instances of RAM and registers which are connected to the word input and output of the RAM. When I synthesize this module though the RAM blocks are't inferred. What must I do to solve this?

Please help with inputs of any kind.

Thanks.