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Setting the clock constraint is fine, but when I need to set the i/p and o/p constraints I need to select each of the 32 write data ports , 8 write and read address ports individually. Is there an easier way of doing this?
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To get valid timing results you have to use the RAM in the style you intend to use it. What you describe is an on-chip RAM instance that has its signals routed to I/O pins. This is probably not how you intend to use this RAM right? What you need to do is create a simplified design with a dual-port RAM instance in it. Then perform a TimeQuest analysis.
To get the maximum performance from an on-chip RAM, you need to enable it to use its input and output registers, drive the input from registers, and capture the output to registers. You can then analyze the timing path from the input registers through the RAM to the output registers.
I'll often create designs using a small Qsys system, eg., per this tutorial
http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial and then either create the new component as a Qsys component, or create another component like your RAM that you can read or write to using say PIO. You can always cut the timing paths from the Qsys system to the input/output registers to isolate the path from TimeQuest analysis. Depending on how you do this, your design might not actually function correctly, but the timing results will be correct, i.e., TimeQuest will tell you what the delays are between the registers in the design.
Note however that you're getting a little too focused on one aspect of the FPGA. Designs can not run on RAM alone. You're better off to come up with a simplified design and check the timing on that.
Cheers,
Dave
Honored Contributor
