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Altera_Forum
Honored Contributor
13 years agoHi rbugalho,
I got what you are saying. I tried it. However I have a question.. I have synthesized a simple dual port ram having 32x8 depth and width. I use the TimeQuest Timing Analyser wizard to set the clock, input and output constraints. Setting the clock constraint is fine, but when I need to set the i/p and o/p constraints I need to select each of the 32 write data ports , 8 write and read address ports individually. Is there an easier way of doing this? Looking forward to your answer. Thanks.