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Altera_Forum
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16 years ago

Frequency of DCLOCK

Hi, I am using ARRIA II GX FPGA with MAX II CPLD. For Active Serial and Fast Passive Parallel (FPP) configurations, what should be the frequency of D_CLK? On what other factors will this clock ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

It's in the datasheet. Before designing with FPGAs, check the datasheet first.

Good luck with your design, Ton