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Altera_Forum
Honored Contributor
Honored Contributorfrequency divider
i want ot create frequency divider which devide the frequency by 50 000 000 (so with 50 MHz clock i want ot reach 1 HZ (T=1s)) can i use this code:
library ieee;
use ieee.std_logic_116...
Altera_ForumHonored Contributor
Honored Contributorso i think in amilcar example the half time must be 25 000 000 (i want from 50 MHz to reach 1 hz ) but i do not have fpga module and i do not know how to simulate frequency devision ?
any tips ?
