Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorfrequency divider
i want ot create frequency divider which devide the frequency by 50 000 000 (so with 50 MHz clock i want ot reach 1 HZ (T=1s)) can i use this code:
library ieee;
use ieee.std_logic_116...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Oh, and do not forget Altera likes async resets. --- Quote End --- It's suggested by the FPGA core architecture, available without requiring additional LE input terms, but you are free to prefer synchronous resets in your designs. Some complex Altera MegaFunctions only provide a synchronous reset - without an explicite specification in the user manual.
