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Altera_Forum
Honored Contributor
Honored Contributorfrequency divider
i want ot create frequency divider which devide the frequency by 50 000 000 (so with 50 MHz clock i want ot reach 1 HZ (T=1s))
can i use this code:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter is
port (CLK, RST :in std_logic;
devided_clk : out std_logic;
Q :out std_logic_vector(16 downto 0)
) ;
end counter;
architecture beh of counter is
signal QL : std_logic_vector (16 downto 0);
begin
process(CLK, RST )
begin
if (CLK'event and CLK = '1')
then if RST='1'
then QL <= "00000000000000000"; devided_clk<= '0';
else if (QL = "11101110011010110010100000000") then QL <= "00000000000000000"; devided_clk <= '1'; else
devided_clk <= '0';
QL <= QL+1;
end if;
end if;
end if;
end process;
Q <= QL;
end beh;
5 Replies
Altera_Forumso i think in amilcar example the half time must be 25 000 000 (i want from 50 MHz to reach 1 hz ) but i do not have fpga module and i do not know how to simulate frequency devision ?
any tips ?- Altera_Forum
I did not calculate the constant, I just reused your value.
BTW you can replace "000000000" with "(others => '0')" And you can write your constant Like this: constant CLK_PERIOD_NS = 20; -- CLK period in [ns] units constant DESIRED_PERIOD_NS = 1000000000; -- desired period in [ns] units constant TIMER_RELOAD = DESIRED_PERIOD_NS/CLK_PERIOD/2-1; And then just replace "11101110011010110010100000000" with TIMER_RELOAD - Altera_Forum
so with amilcar's code the time between two positive jumps (0->1) will be 1 sec ?
- Altera_Forum--- Quote Start --- Oh, and do not forget Altera likes async resets. --- Quote End --- It's suggested by the FPGA core architecture, available without requiring additional LE input terms, but you are free to prefer synchronous resets in your designs. Some complex Altera MegaFunctions only provide a synchronous reset - without an explicite specification in the user manual.
- Altera_Forum
This code is better and simpler. Oh, and do not forget Altera likes async resets (unlike Xilinx). But you should sync the reset signal (it should be the output of a CLK clocked register).process(CLK, RST) begin if RST then QL <= "11101110011010110010100000000"; devided_clk<= '0'; elseif (CLK'event and CLK = '1') then if QL == "00000000000000000" then // comparison with zero is cheaper QL <= "11101110011010110010100000000"; // half count reached, reload devided_clk <= ~devided_clk; // toggle output else QL <= QL - 1; // decrement instead of increment end if; end if; end process;
