Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

frequency divider

i want ot create frequency divider which devide the frequency by 50 000 000 (so with 50 MHz clock i want ot reach 1 HZ (T=1s)) can i use this code: library ieee; use ieee.std_logic_116...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago


process(CLK, RST) begin
  if RST then
    QL <= "11101110011010110010100000000";
    devided_clk<= '0';
  elseif (CLK'event and CLK = '1') then
    if QL == "00000000000000000" then         // comparison with zero is cheaper
      QL <= "11101110011010110010100000000";  // half count reached, reload
      devided_clk <= ~devided_clk;            // toggle output
    else
      QL <= QL - 1;                           // decrement instead of increment
    end if;
  end if;
end process;

This code is better and simpler. Oh, and do not forget Altera likes async resets (unlike Xilinx). But you should sync the reset signal (it should be the output of a CLK clocked register).