Free on-line C to FPGA software

Hi Nadav,

If you look at most of altera/xilinx IPs ,I am sure you will find out that they have clk-enable signal(also called output-enable). At register level, this signal ideally should be routed to the enable port of flipflops. Many projects run at one or few clocks but flexible different rates controlled by this clk-enable. In fact many designers use a pull or push architecture where a module decides the processing rate for adjacent module.If say my system needs to get an fft output at a rate decided by my requesting module then I must control the fft processing not just by the clock but also be able to freeze until next active clock otherwise I have to save all fft block then draw up data as required.