Free on-line C to FPGA software

I had a quick look at the basic ideas of c-to-verilog tool. What I would have preferred to see, a tool that takes care of resource-speed tradeoff. However the tool's module interface is based on free-running default sampling clock. This implies that it can only produce designs sampling on this clock.

Is there any way you can enter a clock enable signal to control processing for selected samples. This is very helpful for two reasons:

-To constrain the module within the system's data flow srchitecture, otherwise the designer will nee extra memory to hold results.

- Can be exploited to make the resource-speed tradeoff.