FPP Configuration Timing: Data stability requirement when DCLK-to-DATA[] ratio > 1

Hello Alex,

Correct - we are concerned about data glitches between rising edges of DCLK: Each rising edge of DCLK would sample idential DATA[] for each DCLK 1..r (with setup and hold times conforming to Figure 7-2), however, the falling edges would not necessarily sample identical DATA[].

Your suspicion that this should work agrees with ours - we were just hoping that this could be confirmed in a more 'official' way in order for us to finalise our H/W design (which currently uses this method as the primary configuration mechanism) with more confidence.

Thanks,

Bernhard