Forum Discussion
Altera_Forum
Honored Contributor
9 years agoI'm not sure I understand your description...
--- Quote Start --- Would it be allowable to implement r>1 using the r=1 timing shown in Figure 7-2 but (indentically) repeating DATA[] r times? --- Quote End --- Isn't the net result the same as holding the data for the required r>1 tDH duration? If you're repeating the same data r times isn't the data static? If you're concerned about glitches occurring on the data then providing the glitches are "away from" (a loose phrase, I know) the rising edge of DCLK and stable again prior to the next rising edge (considering tDSU) I'd expect all to be well. --- Quote Start --- Assuming that DATA[] is only clocked into the device on the rising edge of DCLK --- Quote End --- I'm sure this will be the case. However, by requiring the data to be 'static' for the period specified, the device is clearly 'reserving the right' to sample or re-sample the pins on any rising edge of DCLK. Cheers, Alex