Altera_ForumHonored Contributor9 years agoFPP Configuration Timing: Clock Stop = high We would like to configure a Cyclone V GX C5 using FPP via a TI DSP's EMIFA (External Memory Interface) bus (in Asynchronous mode). VC-52007 2015.12.21 Figure 7-3 mentions in note (5): If needed, pau...Show More
Recent DiscussionsWill serialization factor of 6 in LVDS serdes IP be supported in the future on Agilex5?System PLL of Agliex5 PCIE example design cannot be locked after configurationJTAG Chain Broken on Agilex 7-I Dev KitRequest for Cyclone V Pinout File InformationCyclone 10 LP's Extended Industrial parts