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Altera_Forum's avatar
Altera_Forum
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12 years ago

FPP configuration of Arria V

Hello

I intend to configure my Arria V GX device using Cypress FX3 USB device controller. A previous project here (FX2, Stratix III) did this the very same way, using data[7:0] for configuration first and afterwards doing data transfer over the same I/F in user mode.

Now the challenge is, that according to the manual, data[4:0] have no user I/O function, once the configuration has completed. So I have to bring in another 5 pins for the user data transfer. Finally my interface looks like data[15:0] during configuration, data[15:5] & userdata[4:0] in regular use. As I don't have spare FX3 I/O's, I indent to connect io[4:0] to data[4:0] and userdata[4:0]

Now my questions:

Is there any problem for the userdata[4:0] being driven during FPGA configuration?

Is there any problem for the data[4:0] being driven in user mode?

Is there any ongoing literature on how to do such things?

Thanks!

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    In meantime, I got help from an Altera service request, this is what they answered:

    Q: Is there any problem for the userdata[4:0] being driven during FPGA configuration?

    A: No. Custom I/O pin assigned to replace the 5 dedicated pins (data[4:0]) will not affect the configuration process.

    Q: Is there any problem for the data[4:0] being driven in user mode?

    A: No. For the FPP data pins once the device is in usermode (CONF_DONE is high) the device will ignore any data that is sent on the DATA lines.