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SJadh1's avatar
SJadh1
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7 years ago

fPLL loose lock debug help request

Hello, I am using Arria 10 GX FPGA Development board. I am debugging a fPLL lock issue. In current design fPLL instance gets reference clock from the recovered clock of transceiver. CDR block of...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
Icon for Frequent Contributor rankFrequent Contributor
7 years ago
Hello Sachin, Can you check the pll_cal_busy status ? if it is High can you disable the cal and check the same? Also can you send me the fPLL setting with input and output Frequency ? Thank you, Regards, Sree