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SFP modules are AC coupled (inline capacitors within the module) by design. Driving the SFP using two single ended outputs in a pseudo-differential mode can be made to work (especially at lower signal bandwidths like 100Mb ethernet or 155Mb OC3). Once you get to 622Mb OC12 or higher using this mode is not likely to work well.
Receiving however is a different matter. Since the signals are AC coupled, at the SFP pins you will see single ended signal swings around 0V DC (like -1V to +1V). These levels are not within the valid input range for a single ended receiver, which will be 0V to some VCCIO like 3.3V/2.5V/1.8V. You must terminate the signals in the correct line impedance (ie, 40 to 80 ohms, depending on layout) to maintain signal quality, AND add a DC offset to move the signal into the switching range of the receiver.
Typical boards that interface to SFP modules have resistive termination circuits that perform the termination/restore to (usually) 100ohm differential and a Vt that depends on the receiver, typically this is VCCIO-1.2V or so.
So I think you need to rethink your board design. Just connecting an SFP module to single ended I/O on the FPGA with no external signal conditioning circuit will not work.
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Hi,
Thanks for your reply.
As per your guideline, i have designed breakout board for LVDS driver and signal conditioning.
Here i need clarification in the design. This LVDS driver will be 100ohm impedance. I would like to know, whether both FPGA differential IO pin and SFP transceiver pins are 100ohm impedance or different impedance.
I have attached schematic of the breakout.
Please verify, whether it is ok or not.?
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