FPGA-to-HPS bridge, too slow?

Hi, to answer the question. We had a FOR loop running on the HPS and it toggled a bit in a register on the FPGA side. There was no delay in the FOR loop, the executed as fast as it could. We tide the register bit to a test point where we could look at it on an oscope. We measured a 50% duty cycle square wave but the frequency was something near 16Mhz. The HPS clock was 100Mhz. Remember, that I did not work on this design, I'm only a by-stander relaying information. My main goal with this post is to get feedback from the community with their experiences with the bridge and how fast can one write to a register on the FPGA side from the HPS side. Hope this helps and if anyone has comments, please send them.