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Altera_Forum
Honored Contributor
Honored ContributorFPGA to HPS Bridge access
Hello everyone, I've been trying to send data from FPGA to HPS. I have a few soft IP cores in the FPGA and I want the HPS to read signal data from one of these cores (2 signals of 16 bit width...
Altera_ForumHonored Contributor
Honored ContributorHi. Thanks for your response.
# 1 I think exporting into the top level module would be easier. # 2 Could you please elaborate this point? I have made sure in the Qsys design it is connected to a valid clock. But how do I read values from a particular fpga peripheral address ? Would I need to use something like alt_read_word() function from the socal.h file? If so, then I would have to map the address? For example, would this be the right way to do it? uint32_t signal_value = alt_read_word (f2h_base_address + peripheral_address) Thanks again!
