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SanaGuezguez's avatar
SanaGuezguez
Icon for New Contributor rankNew Contributor
5 years ago

FPGA to HPS and vice versa Communication for Cyclone V

Hello everyone, I'm having an issue implementing an FPGA to HPS communication and vice versa. I'm using the MitySOM 5csx with a Cyclone V SoC. The purpose of the project is to setup the bridges bet...
SanaGuezguez's avatar
SanaGuezguez
Icon for New Contributor rankNew Contributor
5 years ago

Hi,

I'm using Quartus 17.1.
Here is the error : " Error (169281): There are 375 IO input pads in the design, but only 331 IO input pad locations available on the device. "

attached you can find 2 screenshots (part1 and part2) of my QSYS design anf the vhd file for the pin instantiation.

EBERLAZARE_I_Intel's avatar
EBERLAZARE_I_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi,

Seems like it is a IO limitation issue in your design based on the board that you are using. There are too many IO input which is not supported which the device that you are using.

Firstly, can you re-check the Pin Planner to make sure the IO location assignments are set correctly.

Next, you could try to reduce the IO input pads in your design and recompile the design to see if that would work for your board.