FPGA Stratix II Pin assignment and control panel

Hi Dave,

I very new in using tcl console.

I am trying to run the synthesis script but every time I receive an error

These are the steps that I carried out:

1- I have put the four files (s2_dsp,hex_display,synth,pinout) together in one folder and called it s2_dsp

2- Created a Quartus project with name "s2_dsp"

3- In the tcl console I wrote tcl> source synth.tcl

Am I missing any steps ?

This is the ERROR that I receive each time:

source synth.tcl

Synthesizing the S2-DSP 'basic' design

--------------------------------------

- Creating the Quartus work directory

- Creating the VHDL files list

Error:ERROR: Can't open project: s2_dsp

Error: while executing

Error:"project_new -overwrite "s2_dsp""

Error: (file "synth.tcl" line 64)

Error: invoked from within

Error:"_source synth.tcl"

Error: ("uplevel" body line 1)

Error: invoked from within

Error:"uplevel 1 $cmd "

Error: (procedure "source" line 5)

Error: invoked from within

Error:"source synth.tcl"

Thanks,

Mourad