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Altera_Forum's avatar
Altera_Forum
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11 years ago

FPGA reset asynchronous or synchronous?

I normally reset all my d-types using their asynchronous input. I have done this for a long time without any issues. The other day I was chatting to someone else and he said it is best practic...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Ok thanks. I imagine some tricky ways could be done such as switching off D inputs at some level and applying tristate on reset signal at source.