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Altera_Forum
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11 years ago

FPGA reset asynchronous or synchronous?

I normally reset all my d-types using their asynchronous input. I have done this for a long time without any issues. The other day I was chatting to someone else and he said it is best practic...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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Sorry, could you elaborate what you mean by gating?

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For synchronous reset the reset signal is ANDed with D input such that either D passes or reset value. This is required per each flip.

So whether a lab wide route is available or not this gating will be needed (unlike wiring rst to the async port)