FPGA PLL Megafunction

Thank you for your answer, I really Appreciate the Help,

Thanks for the tip "bfkstimchan", Tanks to you now I know i'm not using the wrong PLL

Yes "nic_@ ", I've done it and added the PLL.vhd file which was generated and then I succeffully added the PLL to the top level by writing a structural code of my project. Thank you, it confirms what I thought about the creation of the PLL Megafunction.

I followed what you said "Bhaumik" I added the libraries you talked about, but I still have an error occuring during the RTL compilation, telling me that this is a nativelink error and that it failed to make the ip-make-simscript.

I can simulate my all-pass filter witout problems but not my PLL alone and not my complete design.

I don't know if you can help me on this one, i don't know where the problem is from.

Anyway I think the PLL work, once I implement the binary file in the FPGA I see some differences. But It would be better to be able to simulate it before implementing it in the device...

Thank you all !

David.