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jasonkee111's avatar
jasonkee111
Icon for New Contributor rankNew Contributor
4 years ago

FPGA Lock Time and Cascading PLL

Hi I do have some questions about PLL: 1. If the same reference clock is connected to 2 PLLs in a device, does the lock time will be the same? These 2 PLL output clock are in sync? 2. If t...
Farabi_Altera's avatar
Farabi_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hello,


I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


regards,

Farabi