FPGA load on cyclone V GSRD

Hi Shoval,

May I know did you perform the cmd "bridge enable" in UBoot after the FPGA hardware design has been loaded?

When you open GHRD with the qsys file in the quartus platform designer. You can see the sysID(System ID Peripipheral IP) with the data of 0xacd51500 when open the parameters of that IP.

Based on the system design connections referring to the IP address assignment, you can use the cmd "md" after "bridge enable" in Uboot (md 0xFF460008) to check the expected sysID data is 0xacd51500. This will help to check the design has been loaded into the FPGA fabric through LWHPS2FPGA AXI Bridge Module(h2f_lw_axi_master) with the HPS memory address of 0xFF400000:

https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html

Thanks.

Regards,

Aik Eu