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prabu's avatar
prabu
Icon for New Contributor rankNew Contributor
3 years ago

FPGA IP related clarification in Quartus 13 version

Hi Team, We are using Cyclone III EP3C40F484C6 device 13.0 version in our project. It is updated from old design that is 9.1 version. In design , for pwm control accumulator IP is used in 9.0 versi...
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FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
3 years ago

Sorry I misunderstood the question. Quartus 13 clearly states that altaccum is no longer available.

You can either use altaccum design files generated in Quartus 9, or instantiate alt_add_sub with 1 cycle pipeline delay and feed back the output to input a.