FPGA Impementation Digital Clock

--- Quote Start ---

What you have done isnt really VHDL - you've just created a netlist of components. You can do much better looking stuff in vhdl like this:

signal minute : integer range 0 to 59;
signal hour : integer range 0 to 23;
 
process(clk)
begin
  if rising_edge(clk) then
    if progress_minute then
      if minute = 59 then
        minute <= 0;
 
        if hour = 23 then
          hour <= 0;
        else
          hour <= hour + 1;
        end if;
      else
        minute <= minute + 1;
      end if;
    end if;
  end if;
end process;

--- Quote End ---

Thank for your reply...

If i want to design by using structural how should i write???