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Altera_Forum
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11 years ago

FPGA Hard Memory Controller ODT Pin

We are connecting two DDR3 SDRAM ICs to a Cyclone V 5CEFA9F31. Our application only requires one ODT signal. However, there are two hard memory controller pins (T_ODT_0 and T_ODT_1). Can we use eithe...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

The dramodt section on pages 4-45 and 4-46 in the External Memory Interface Handbook Volume 3 seems to indicate that any combination of ODT[0] and ODT[1] can be configured to be asserted for CS0 and CS1. Is that correct?