Forum Discussion

Honored Contributor

11 years ago

FPGA Hard Memory Controller ODT Pin

We are connecting two DDR3 SDRAM ICs to a Cyclone V 5CEFA9F31. Our application only requires one ODT signal. However, there are two hard memory controller pins (T_ODT_0 and T_ODT_1). Can we use eithe...

Altera_Forum

Honored Contributor

11 years ago

The dramodt section on pages 4-45 and 4-46 in the External Memory Interface Handbook Volume 3 seems to indicate that any combination of ODT[0] and ODT[1] can be configured to be asserted for CS0 and CS1. Is that correct?

Forum Discussion

FPGA Hard Memory Controller ODT Pin

Recent Discussions

Avalon-ST configuration with Agilex 3 fails

Cyclone IV E – PLL Power Track Width Recommendation Clarification

Operating temperature for 10M08DCF256A7G

System PLL of Agliex5 PCIE example design cannot be locked after configuration

Download links not working