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Altera_Forum
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12 years ago

FPGA external reset

hi， I am using Cyclone III,and I'd like to have my own external reset.but I am not sure when to safely insert external reset ASAP. Do I have to use it after CONF_DONE goes high? i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Mux and Dave,thanks a lot. it's a new design,I plan to route CONF_DONE to reset supervisor manual input. The "standard" gives me more confidence:_),although I noted http://www.ovro.caltech.edu/~dwh/car...0.87_dec03.pdf is mentioned several times in different threads.

I still want to figure out how to understand "all I/O are tri-stated when configuration", Does it mean external POR can't enter FPGA when configuration, or it enters,but has no effect on FPGA configuration? can you help with this?