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Altera_Forum's avatar
Altera_Forum
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12 years ago

FPGA external reset

hi， I am using Cyclone III,and I'd like to have my own external reset.but I am not sure when to safely insert external reset ASAP. Do I have to use it after CONF_DONE goes high? i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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If the reset supervisor has a pin for that :-) I used a cheapo TO-92...

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Sure, for an existing design you can't really do much, but for a new design, its a nicer way to ensure your FPGA is held in reset until it enters user mode.

NOTE: you still need reset synchronizers internal to the FPGA for each of your clock domains.

Cheers,

Dave