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Altera_Forum's avatar
Altera_Forum
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15 years ago

Fpga ethernet voltage levels

Hey everybody, I am transmitting ONLY from the FPGA without PHY chip ( are implemented the basic PHY functions on the FPGA ), also i am using isolation ( transformer ). The fpga Cyclone I ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Using impedance matching resistors already creates a 1:1 divider. If you want to lower the voltage further, use a divider instead of series resistors. It should have 50 ohm single ended/ 100 ohm differential output impedance towards the filter/transformer.

I don't see a problem. It's basically the same technique used for 3R LVDS resistor networks.