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Altera_Forum's avatar
Altera_Forum
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15 years ago

FPGA device Startup: Reset

When power up the FPGA device, will it automatically reset the device without any controlling?

If yes, the reset signal is sent through global reset pin on working internally? Besides, what is the period of reset pulse? Can the period of reset pulse be controlled?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hello,

    short answer: it's automatic, internal and you can't control the period.

    First, after power up the FPGA does a "power on reset" cycle.

    Second, after that, it needs to be configured. There are several ways to configure an FPGA but in the most common one (Active Serial), the FGPA will automatically read it's configuration from a EPCS flash memory.

    After the FPGA has been configured, the design is loaded and initialized.

    a) Registers are initialized to zero, unless you specify otherwise*.

    b) Memory blocks are initilized to zero, unless you specifiy otherwise.

    * Actually, physical registers are always intialized to zero. But if you specify that a register has to be initilized to "1", the synthesis tools will use a technique called "not gate push back" to make the design behave as such.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Note that the reset holds all registers in the reset state until after configuration is done, and then releases the device. There is no timing analysis on this release(as it's probably slow and not related to any clock domains in the user's design) and should not be relied on for safe recovery. The user should have their own domain-wide resets. An asynchronous assert, synchronous de-assert is generally recommended since it can be timed. I posted a document called "Understanding Recovery and Removal in TimeQuest" that hopefully helps.

    http://www.alteraforum.com/forum/showthread.php?t=5026
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Hi,

    This is with regard to Cyclone-IV E FPGA configuration cycle.

    Configuration cycle consists 3 statges. They are a. Reset b. Configuration c. Initialization.

    After initialization, user mode will start.

    Now, do I need to give reset signal to FPGA externally to give reset to 'user implemented logic' in FPGA to get defined state of the registers inside FPGA in user mode ?

    Or is it automatically be done during intialization stage of the configuration cycle ?

    Please clarify.

    Regards,

    Thulasi