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Honored Contributor
Honored ContributorFPGA device Startup: Reset
When power up the FPGA device, will it automatically reset the device without any controlling? If yes, the reset signal is sent through global reset pin on working internally? Besides, what...
Altera_ForumHonored Contributor
Honored ContributorHi,
This is with regard to Cyclone-IV E FPGA configuration cycle. Configuration cycle consists 3 statges. They are a. Reset b. Configuration c. Initialization. After initialization, user mode will start. Now, do I need to give reset signal to FPGA externally to give reset to 'user implemented logic' in FPGA to get defined state of the registers inside FPGA in user mode ? Or is it automatically be done during intialization stage of the configuration cycle ? Please clarify. Regards, Thulasi
