FPGA device Startup: Reset

Note that the reset holds all registers in the reset state until after configuration is done, and then releases the device. There is no timing analysis on this release(as it's probably slow and not related to any clock domains in the user's design) and should not be relied on for safe recovery. The user should have their own domain-wide resets. An asynchronous assert, synchronous de-assert is generally recommended since it can be timed. I posted a document called "Understanding Recovery and Removal in TimeQuest" that hopefully helps.