FPGA Development Board - strange shift operation behavior

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Not sure what you mean by this. led[11:0] is a register, so you can access it at any time in any logic equation within that module. The value will only change when the always block that encloses it is triggered and the value is updated.

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Code example:

reg  value;
reg  circle_count;
reg  count;
always @(posedge clk)
begin
    count <= count + 1'b1;
    if (count == 1) begin    
        count <= 0;
        circle_count <= circle_count + 1'b1;
        if (circle_count == 12)
            circle_count <= 0;        
    end
end
always @(circle_count)
begin
    case (circle_count)
        0: value <= 5'b00101;
        1: value <= value; // 5'b00101
        2,3,4: value <= (value << 1); // always 0 - why? 
// When I start simulation test - it will changes succesfully
// On Board - it always ZERO when I try to shift it.
        default: value <= 12'b10101;
    endcase
end
endmodule