FPGA Development Board - strange shift operation behavior

reg  led;
reg  circle_count;
...
always@(circle_count or led) begin
  if (circle_count == 4'd0) begin
    led = BASE_LED_SEQUENCE;
  end
  else begin
    led = led << 1;
  end
end

This is very inefficient logic for variables defined as registers. You have built a change detector on circle_count[3:0] that will trigger an asynchronous clocking of the led[11:0] registers when it triggers.

Why not just add the statement:

led <= circle_count == 4'd0 ? BASE_LED_SEQUENCE : led << 1;

into the main loop, so it looks like this:

always @(posedge clk or negedge reset)
    begin
    if (!reset) 
        begin
        count <= 28'd0;
        circle_count <= 4'd0;
        led <= 12'b0;
        end
    else
        begin
        if (count == 1'b1)
            begin    
            count <= 28'd0;
            circle_count <= circle_count == 4'd12 ? 4'd0 : circle_count + 4'd1;
            led <= circle_count == 4'd0 ? BASE_LED_SEQUENCE : led << 1;
            end
        else
            count <= count + 28'd1;
        end
    end

which I think is a lot easier to follow.