FPGA Development Board - strange shift operation behavior

Try this one and check, it runs in my simulations..

module led4_reg(clk, reset, led);
parameter BASE_LED_SEQUENCE = 12'b000011101101;
input clk;
input reset;
output  led;
reg  led;
reg  circle_count;
//wire  led_tmp;
//initial begin
//    led = 0;
//    count = 0;
//    circle_count = 0;
//    led <= ~led;
//    $monitor($time, " led = %b count = %d", led, circle_count);
//end
reg  count;
always @(posedge clk or negedge reset)
begin
    if (!reset) 
	 begin
	     count        <= 28'd0;
		  circle_count <= 4'd0;
    end
	 else begin
        count <= count + 28'd1;       
        circle_count <= circle_count + 4'd1;
    if (circle_count == 4'd12)
        circle_count <= 4'd0;        
    end
end
always@(circle_count or led) begin
  if (circle_count == 4'd0) begin
    led = BASE_LED_SEQUENCE;
  end
  else begin
    led = led << 1;
end
end
endmodule